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-- Company: 
-- Engineer:
--
-- Create Date:   23:55:17 06/05/2010
-- Design Name:   
-- Module Name:   C:/Users/Tom/Documents/lcpd-scope/vhdl/project/Trigger_Test_Bench.vhd
-- Project Name:  LCPD_Scope
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Trigger_Module
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY Trigger_Test_Bench IS
END Trigger_Test_Bench;
 
ARCHITECTURE behavior OF Trigger_Test_Bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Trigger_Module
    PORT(
         Data_A_in : IN  std_logic_vector(11 downto 0);
         Data_B_in : IN  std_logic_vector(11 downto 0);
         Data_A_out : OUT  std_logic_vector(11 downto 0);
         Data_B_out : OUT  std_logic_vector(11 downto 0);
         Trigger_out : OUT  std_logic;
         Trigger_level_in : IN  std_logic_vector(11 downto 0);
         Trigger_A_B : IN  std_logic;
         Trigger_Edge : IN  std_logic;
         Trigger_Mode : IN  std_logic;
         reset_in : IN  std_logic;
         newdata_in : IN  std_logic;
         newdata_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Data_A_in : std_logic_vector(11 downto 0) := (others => '0');
   signal Data_B_in : std_logic_vector(11 downto 0) := (others => '0');
   signal Trigger_level_in : std_logic_vector(11 downto 0) := (others => '0');
   signal Trigger_A_B : std_logic := '0';
   signal Trigger_Edge : std_logic := '0';
   signal Trigger_Mode : std_logic := '0';
   signal reset_in : std_logic := '0';
   signal newdata_in : std_logic := '0';

 	--Outputs
   signal Data_A_out : std_logic_vector(11 downto 0);
   signal Data_B_out : std_logic_vector(11 downto 0);
   signal Trigger_out : std_logic;
   signal newdata_out : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Trigger_Module PORT MAP (
          Data_A_in => Data_A_in,
          Data_B_in => Data_B_in,
          Data_A_out => Data_A_out,
          Data_B_out => Data_B_out,
          Trigger_out => Trigger_out,
          Trigger_level_in => Trigger_level_in,
          Trigger_A_B => Trigger_A_B,
          Trigger_Edge => Trigger_Edge,
          Trigger_Mode => Trigger_Mode,
          reset_in => reset_in,
          newdata_in => newdata_in,
          newdata_out => newdata_out
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
  -- constant <clock>_period := 10 ns;
 
   newdata_in_process :process
   begin
		newdata_in <= '0';
		wait for 5 ns;
		newdata_in <= '1';
		wait for 5 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
			Trigger_level_in <= "100000000000";
			Trigger_A_B <= '1'; -- Channel A
			Trigger_Edge <= '1'; -- Rising Edge
			Trigger_Mode <= '0';
			reset_in <= '0';
			Data_A_in <= "011111111111";
			wait for 10 ns;
			Data_A_in <= "111111111111";
			wait for 100 ns;

      -- insert stimulus here 

      wait;
   end process;

END;
